Bipolar structure with two base-emitter junctions in the same circuit

ABSTRACT

Bipolar integrated circuits employing SiGe technology incorporate the provision of mask-selectable types of bipolar transistors. A high-performance/high variability type has a thin base in which the diffusion from the emitter intersects the base dopant diffusion within the “ramp” of Ge concentration near the base-collector junction and a lower performance/lower variability type has an additional epi layer in the base so that the emitter diffusion intersects the Ge ramp where the ramp has a lower ramp rate.

TECHNICAL FIELD

[0001] The field of the invention is that of bipolar transistors, inparticular transistors using Si and Ge.

BACKGROUND OF THE INVENTION

[0002] It has been found that, in order to create a high performanceSiGe bipolar transistor, the Ge profile in those transistors has to havea rapidly increasing concentration, or “ramp”, from a low concentrationin the vicinity of the emitter-base junction to a higher concentration(e.g. 20-30% mole fraction) within the neutral base of the device. Anincrease in the Ge concentration creates a change in the band structureof the crystal, which defines an electric field across a portion of theneutral base. This electric field substantially accelerates the carriersto cross the device in a short time, and thus improves the highfrequency gain of the device.

[0003] Thus the need to improve switching speed has driven an increasein the ramp rate, in order to increase the electric field in the neutralbase, accelerating the carriers to high velocity in as short a distanceas possible. As is also well known, a second effect of the Ge at theemitter-base junction is to reduce the conduction band potential at thatlocation, and thus increase the quantity of electrons injected from theemitter into the neutral base. This electron injection comprises thecollector current, which is a quantity that needs to be well controlledso that the behavior of the bipolar device, and thus the performance ofthe circuit, is predictable. The complicating factor is that the emitterjunction depth is variable with normal process variations (e.g., emitterand base dopant concentration variation, interface variability, andtemperature repeatability and uniformity).

[0004] Relative to the Ge ramp, the process variations in theemitter-base junction depth result in variations in the Ge percentage atthat junction location, and thus collector current is found to bevariable. Because the dependence of collector current on Ge percentageis exponential, this effect is observed to be large (at least a range of+−50 percentage of the nominal value).

[0005] Thus there is a tradeoff. Higher Ge ramp rates increase the speedof the bipolar transistor, yet the same higher ramp rates increase thevariability of the collector current in the device.

[0006] There remains a need for providing the designers an option toimprove tolerance.

[0007] It is well known that performance may be traded off withcollector avalanche and breakdown voltage through mask-selectablemodifications in collector design on the same chip. Commonly, this isaccomplished through implantation through or before the epitaxy layer,or blocking this implant with a photoresist layer. Other inventors haveseen appropriate to form completely different base epitaxy regions on achip, through mask-selectable regions of exposed single-crystalcollector prior to epitaxy growth. The base epitaxy in such a solutionincludes different collector, base, and emitter regions. Such a solutionhas drawbacks of process complexity resulting from the multiple criticalfilm growth, longer process times from the lengthy growth of relativelythick films, and process control issues resulting from the completelyseparate devices.

SUMMARY OF THE INVENTION

[0008] The invention relates to bipolar transistors using Si-Gematerial.

[0009] A feature of the invention is the presences of two types ofbipolar SiGe transistor in the same integrated circuit.

[0010] Another feature of the invention is a mask-selectable alternatebase-emitter junction.

[0011] Another feature of the invention is a high performance/poortolerance device structure, having a base dopant of a lower total dose,and an emitter diffusion that intersects the base dopant within thesteep germanium ramp.

[0012] Yet another feature of the invention is a lowperformance/improved tolerance device structure, in which the basedopant has a greater total dose and the emitter diffusion intersects thebase dopant at a more constant (or at zero) germanium concentration.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1a shows a graph of the dopant concentration in a prior artdevice.

[0014]FIG. 1b shows a graph of the dopant concentration in a deviceaccording to the invention.

[0015]FIGS. 2a and 2 b show graphs of the dopant concentration in twoalternative devices according to the invention.

[0016]FIG. 3 shows the result of preliminary steps in fabricating theinvention.

[0017] FIGS. 4-6 show the result of intermediate steps in fabricatingthe invention.

[0018]FIG. 7 shows two completed embodiments of the invention.

DETAILED DESCRIPTION

[0019] This invention provides a mask-selectable alternate base-emitterjunction that provides the designer with an additional choice in tradingoff performance for improved tolerance to process variations. In thecase of a high performance/high variability device structure, the basedopant is of a lower total neutral base dose, (e.g.1×10¹³/cm²-1×10¹⁴/cm²) and the emitter diffusion intersects the basedopant within the steep germanium ramp. This structure provides highperformance, but at the cost of high susceptibility to processvariations because of the exponential dependence of collector current onGe concentration.

[0020] In the case of a low performance/improved tolerance devicestructure, the base dopant has a greater total dose, (e. g. from only10% higher dose to ten time the dose) and the emitter diffusionintersects the base dopant at a more constant (or at zero) germaniumconcentration.

[0021] The structure has a collector that incorporates an epitaxial SiGefilm which is identical between the two devices, except that in thelower performance/improved tolerance device, there is an additionalboron dose nearer to the surface of the original boron dose, and a thin(2-30 nm thick) epitaxial layer added on top of the SiGe film that makesup the higher performance device. The terms improved tolerance (toprocess variations) and lower variability (to process variations) willbe used interchangeably.

[0022] Shown in FIG. 1 is an example profile for a high performancen-p-n SiGe bipolar device. FIG. 1a illustrates the high performancedevice profile which in itself may be viewed as the prior art. Thenotable feature is that the emitter dopant 130 (typically arsenic orphosphorous) is at a depth which overlaps the germanium ramp 110. Thisserves to substantially reduce the transit time of the injected carriersacross the base region of the device. The profile illustrated in FIG.1b, which exists on the same wafer as the profile in FIG. 1a, containsthe same germanium ramp, and the same original boron profile as thatshown in FIG. 1a. Added to the original profile is a thin (2-30 nm)epitaxy layer between vertical lines 35 and 55 and an additional borondopant 120′ that extends the boron curve to the left.

[0023] This combination pushes the emitter junction further from thegermanium ramp (to the left) such that it does not intersect the rampand thus does not have the variable transistor parameters that resultfrom the variable germanium concentration at the location of thejunction with process variations in junction depth.

[0024] Concentration curves for a second embodiment of this inventionare shown in FIG. 2. FIG. 2a shows the data for a high performancestructure and FIG. 2b shows the corresponding data for the lowvariability structure. This curve differs from the prior example in thesource of the additional boron dose. Here, the epitaxy growth includesadditional boron dopant (the portion of curve 125 between lines 35 and55) which is a sufficiently low concentration to be compensated by theemitter dopant in the high performance/poor tolerance device in FIG. 2a,and serves as a base dopant in the lower performance/improved tolerancedevice of FIG. 2b. Thus, the extra boron dose is implanted in the firstembodiment, and deposited during the epitaxy steps in the secondembodiment, yet serves the same function in the two embodiments. Likethe previous example, the emitter-base junction in FIG. 2b does notintersect the germanium on some devices on the wafer, and thus hasimproved control.

[0025] The important aspect of the emitter dopant-Ge overlap is that atthe intersection of the emitter dopant curve and the Ge concentrationcurve, the ramp rate, or change in the Ge concentration, should begreater than a threshold value in the high performance embodiment. Thoseskilled in the art are aware that intersection of the curves at a depth(or vertical location in the structure) where the Ge concentration isconstant as a function of vertical position will not have a significantbeneficial effect on performance. In current processing an appropriatethreshold value is a concentration ramp rate of 5% per 100 Angstroms.Different processes may have slightly different values of the threshold.

[0026] One method to accomplish the previously described structure isnext discussed with respect to FIG. 3. Those skilled in the art willreadily be able, in the light of this disclosure to devise other methodsof providing the structure shown. The initial steps in the transistorfabrication process are the provision of preparation steps, such asblanket doping, forming isolation members to separated devices, padoxide and/or nitride, etc. that will be referred to in the claims aspreparing the substrate. In this case, shallow trench isolation (STI)members 20 have been formed in substrate 10 and a uniform layer of SiGe30 has been put down. The SiGe film typically contains both the borondopant 120 of FIG. 1a and the Ge ramp profile 110 of FIG. 1a. It iscommonly found that a SiGe film is deposited across the wafer (i.e.,blanket), and grows epitaxially (i.e., with the underlying crystalstructure) through a patterned opening where the NPN transistor will befabricated, and polycrystalline in other areas. The SiGe film growth isfollowed by a passivation film growth or deposition, which is commonlysilicon dioxide 40 of approximately 5-20 nm in thickness. Film 40 mayhave deposited on top additional films, such as polycrystalline silicon,which may aid later process steps, and for simplicity purposes are notshown here. This structure, including the shallow-trench isolation, isshown in FIG. 3.

[0027]FIG. 4 shows an example of insulating film 40 which has beenpatterned with photoresist to form an opening denoted by bracket 42 overthe lower performance/improved tolerance device (denoted generally bynumeral 80), and where the insulating film 40 has been etched down tothe silicon surface, and the resist removed. On the right in the Figure,numeral 70 denotes generally the area where the higher performancetransistor will be formed.

[0028]FIG. 5 shows these areas following the epitaxial deposition of thesecond (silicon) epitaxy film, where this film forms as single crystalover the lower performance/improved tolerance device, and may form aspolycrystalline silicon over the insulating film. Alternatively, thesecond epitaxy film may be grown as a selective epitaxy, where the filmis grown only over the insulating film opening. At this point, a blanket(unmasked) boron implant may be applied to form the additional basedopant 125 shown in FIG. 1b. Following this step, a photoresist isapplied and the epitaxy film and the insulating film are removed inregions except the regions 80 of the lower performance/improvedtolerance device, as shown in FIG. 6.

[0029] At this point, the surface of both device types is exposed, andprocessing can continue with standard passivation, dielectric films, andemitter film deposition and patterning. The result is shown in FIG. 7,with top surface 35 of SiGe film 30 and top surface 55 of silicon film50 (having the dopant concentration shown in FIGS. 1 and 2). Polysiliconemitters 60, with emitter-base isolation defined by dielectric 65 (oxideor nitride) have been formed simultaneously in both transistors. Thusthe two emitters-base junctions are formed.

[0030] The circuit will be completed by patterning the base film 30,providing electrodes to the emitter, base and collector (not shown) andconnecting the transistors according to the particular schematic beingimplemented, by techniques known to those skilled in the art.

[0031] The same first SiGe base epitaxy, collector, and emitter processis used for both transistors. The difference is an additional epitaxylayer on top of the shared SiGe base layer for device 80 which is notpart of the second device 70 and corresponding changes in the dopantdistribution.

[0032] Those skilled in the art will appreciate that variousmodifications can be made to the embodiment illustrated. As one example,the second epitaxy film may be deposited by a selective epitaxy processfollowing the etch of film 65 to form the emitter opening. Selection ofthe emitter-base properties may be made by utilizing two separateemitter opening masks. For generality, the following claims will referto a crystalline silicon layer, independent of the method for maskingand deposition

[0033] Complementary circuits may be fabricated by applying the sametechnique to the construction of PNP bipolar transistors, using theconventional substitution of dopants. The result is a set ofmask-selectable high performance and low variability transistors forboth PNP and NPN versions.

[0034] Those skilled in the art will appreciate that the germaniumprofile may be a constant ramp rate as depicted in FIG. 1, or may be aprofile with different ramp slopes in order to optimize the performanceof the two device types described in this invention.

[0035] While the invention has been described in terms of a singlepreferred embodiment, those skilled in the art will recognize that theinvention can be practiced in various versions within the spirit andscope of the following claims.

What is claimed is:
 1. An integrated circuit comprising a semiconductorsubstrate; a SiGe layer formed on said semiconductor substrate; a firstset of bipolar transistors having a collector; a base formed in a layerof crystalline silicon material which includes a base dopant and Ge andan emitter disposed above and abutting said base, in which an emitterdopant concentration intersects a Ge concentration at a depth into thebase where the ramp rate of said Ge concentration is greater than athreshold value; a second set of bipolar transistors having a collector;a base formed in a layer of crystalline silicon material which includesboron and Ge; an additional layer of crystalline silicon material onsecond set of bipolar transistors, disposed above and abutting saidbase; and an emitter disposed above and abutting said additional layerof crystalline silicon material, in which an emitter dopantconcentration intersects the base at a different location relative tosaid Ge concentration where the ramp rate of said Ge concentration isless than a threshold value.
 2. An integrated circuit according to claim1, in which said Ge concentration at said different location where saidemitter dopant concentration intersects the base is substantially zero.3. An integrated circuit according to claim 1, in which said bases insaid first set and in said second set are formed of a first epitaxiallayer of material and said bases in said second set further comprise asecond epitaxial layer of material, thereby separating said emitter fromsaid SIGe layer by a longer distance.
 4. An integrated circuit accordingto claim 2, in which said bases in said first set and in said second setare formed of a first epitaxial layer of material and said bases in saidsecond set further comprise a second epitaxial layer of material,thereby separating said emitter from said SIGe layer by a longerdistance.
 5. An integrated circuit according to claim 3, in which saidfirst and said second sets of bipolar transistors comprise NPNtransistors.
 6. An integrated circuit according to claim 3, in whichsaid first and said second sets of bipolar transistors comprise PNPtransistors.
 7. An integrated circuit according to claim 3, in whicheach of said first and said second sets of bipolar transistors compriseboth NPN and PNP transistors.
 8. A method of forming an integratedcircuit containing first and second sets of bipolar transistors formedin a SiGe layer comprising the steps of: forming said SiGe layer on asemiconductor substrate; simultaneously forming in said SiGe layer afirst set of collectors for said first set of bipolar transistors and asecond set of collectors for said second set of bipolar transistors;simultaneously forming a first base layer, having a base dopant andfirst base thickness, for said first set of bipolar transistors and forsaid second set of bipolar transistors, said first base layer beingformed in a layer of material having a concentration ramp of Geconcentration in the vicinity of a base-collector junction; forming asecond layer of base material over and abutting said first base layer insaid second set of transistors; and simultaneously forming a layer ofemitter material disposed above and abutting said bases in said firstset and second sets of bipolar transistors, said emitter material havinga concentration curve of emitter dopant extending through at least partof said base so that said concentration curve of emitter dopant in saidfirst set intersects said concentration ramp of said first set in alocation where a concentration ramp rate of said first set is greaterthan a threshold value; and said second layer of base material having athickness such that said second set of transistors have a greaterdistance between a base-emitter junction and a base-collector junction,so that said concentration curve of emitter dopant in said second setintersects said concentration ramp of said second set in a locationwhere a concentration ramp rate of said second set is less than saidthreshold value.
 9. A method of forming an integrated circuit containingfirst and second sets of bipolar transistors according to claim 7, inwhich said greater distance of said second set is such that saidconcentration curve of emitter dopant has a value of substantially zeroat said location.
 10. A method of forming an integrated circuitcontaining first and second sets of bipolar transistors according toclaim 7, in which said step of forming said SiGe layer comprisesdepositing an epitaxial layer of silicon, together with Ge and a basedopant, such that said Ge has a variable concentration that forms saidconcentration ramp and such that said base dopant has a baseconcentration near an upper surface of said SiGe layer.
 11. A method offorming an integrated circuit containing first and second sets ofbipolar transistors according to claim 8, in which said step of formingsaid SiGe layer comprises depositing an epitaxial layer of silicon,together with Ge and a base dopant, such that said Ge has a variableconcentration that forms said concentration ramp and such that said basedopant has a base concentration near an upper surface of said SiGelayer.
 12. A method of forming an integrated circuit containing firstand second sets of bipolar transistors according to claim 7, in whichsaid step of forming said second layer of base material comprisesdepositing a patterned masking layer on said SiGE layer outsidelocations for said second set of bipolar transistors and depositing ablanket layer of said epitaxial layer of silicon.
 13. A method offorming an integrated circuit containing first and second sets ofbipolar transistors according to claim 7, in which said step of formingsaid second layer of base material comprises masking said SiGE layeroutside locations for said second set of bipolar transistors andselectively depositing a layer of said epitaxial layer of silicon inapertures formed in said masking layer.
 14. A method of forming anintegrated circuit containing first and second sets of bipolartransistors according to claim 8, in which said step of forming saidsecond layer of base material comprises depositing a patterned maskinglayer on said SiGE layer outside locations for said second set ofbipolar transistors and depositing a blanket layer of said epitaxiallayer of silicon.
 15. A method of forming an integrated circuitcontaining first and second sets of bipolar transistors according toclaim 8, in which said step of forming said second layer of basematerial comprises masking said SiGE layer outside locations for saidsecond set of bipolar transistors and selectively depositing a layer ofsaid epitaxial layer of silicon in apertures formed in said maskinglayer.
 16. A method of forming an integrated circuit containing firstand second sets of bipolar transistors according to claim 9, in whichsaid step of forming said second layer of base material comprisesdepositing a patterned masking layer on said SiGE layer outsidelocations for said second set of bipolar transistors and depositing ablanket layer of said epitaxial layer of silicon.
 17. A method offorming an integrated circuit containing first and second sets ofbipolar transistors according to claim 9, in which said step of formingsaid second layer of base material comprises masking said SiGE layeroutside locations for said second set of bipolar transistors andselectively depositing a layer of said epitaxial layer of silicon inapertures formed in said masking layer.
 18. A method of forming anintegrated circuit containing first and second sets of bipolartransistors according to claim 9, in which said first and second sets ofbipolar transistors comprise NPN bipolar transistors.
 18. A method offorming an integrated circuit containing first and second sets ofbipolar transistors according to claim 9, in which said first and secondsets of bipolar transistors comprise PNP bipolar transistors.
 19. Amethod of forming an integrated circuit containing first and second setsof bipolar transistors according to claim 9, in which each of said firstand second sets of bipolar transistors comprise both NPN and PNP bipolartransistors.